Advanced Formal Verification
thg 5 2007 · Springer Science & Business Media
Sách điện tử
250
Trang
reportĐiểm xếp hạng và bài đánh giá chưa được xác minh Tìm hiểu thêm
Giới thiệu về sách điện tử này
Modern circuits may contain up to several hundred million transistors. In the meantime it has been observed that verification becomes the major bottleneck in design flows, i.e. up to 80% of the overall design costs are due to verification. This is one of the reasons why several methods have been proposed as alternatives to classical simulation. Simulation alone cannot guarantee sufficient coverage of the design resulting in bugs that may remain undetected.
As alternatives formal verification techniques have been proposed. Instead of simulating a design the correctness is proven by formal techniques. There are different areas where these approaches can be used: equivalence checking, property checking or symbolic simulation. These methods have been successfully applied in many industrial projects and have become the state-of-the-art technique in several fields. However, the deployment of the existing tools in real-world projects also showed the weaknesses and problems of formal verification techniques. This gave motivating impulses for tool developers and researchers.
Advanced Formal Verification shows the latest developments in the verification domain from the perspectives of the user and the developer. World leading experts describe the underlying methods of today's verification tools and describe various scenarios from industrial practice. In the first part of the book the core techniques of today's formal verification tools, such as SAT and BDDs are addressed. In addition, multipliers, which are known to be difficult, are studied. The second part gives insight in professional tools and the underlying methodology, such as property checking and assertion based verification. Finally, analog components have to be considered to cope with complete system on chip designs.
In this book the state-of-the-art in many important fields of formal verification are described. Besides the description of the most recent research results, open problems and challenging research areas are addressed. Because of this, the book is intended for CAD developers and researchers in the verification domain, where formal techniques become a core technology to successful circuit and system design. Furthermore, the book is an excellent reference for users of verification tools in order to acquire a better understanding of the internal principles and subsequently drive the tools to the highest performance. In this context the book is dedicated to those in industry and academia to stay informed about the most recent developments in the field of formal verification.
As alternatives formal verification techniques have been proposed. Instead of simulating a design the correctness is proven by formal techniques. There are different areas where these approaches can be used: equivalence checking, property checking or symbolic simulation. These methods have been successfully applied in many industrial projects and have become the state-of-the-art technique in several fields. However, the deployment of the existing tools in real-world projects also showed the weaknesses and problems of formal verification techniques. This gave motivating impulses for tool developers and researchers.
Advanced Formal Verification shows the latest developments in the verification domain from the perspectives of the user and the developer. World leading experts describe the underlying methods of today's verification tools and describe various scenarios from industrial practice. In the first part of the book the core techniques of today's formal verification tools, such as SAT and BDDs are addressed. In addition, multipliers, which are known to be difficult, are studied. The second part gives insight in professional tools and the underlying methodology, such as property checking and assertion based verification. Finally, analog components have to be considered to cope with complete system on chip designs.
In this book the state-of-the-art in many important fields of formal verification are described. Besides the description of the most recent research results, open problems and challenging research areas are addressed. Because of this, the book is intended for CAD developers and researchers in the verification domain, where formal techniques become a core technology to successful circuit and system design. Furthermore, the book is an excellent reference for users of verification tools in order to acquire a better understanding of the internal principles and subsequently drive the tools to the highest performance. In this context the book is dedicated to those in industry and academia to stay informed about the most recent developments in the field of formal verification.
Xếp hạng sách điện tử này
Cho chúng tôi biết suy nghĩ của bạn.
Đọc thông tin
Điện thoại thông minh và máy tính bảng
Cài đặt ứng dụng Google Play Sách cho Android và iPad/iPhone. Ứng dụng sẽ tự động đồng bộ hóa với tài khoản của bạn và cho phép bạn đọc trực tuyến hoặc ngoại tuyến dù cho bạn ở đâu.
Máy tính xách tay và máy tính
Bạn có thể nghe các sách nói đã mua trên Google Play thông qua trình duyệt web trên máy tính.
Thiết bị đọc sách điện tử và các thiết bị khác
Để đọc trên thiết bị e-ink như máy đọc sách điện tử Kobo, bạn sẽ cần tải tệp xuống và chuyển tệp đó sang thiết bị của mình. Hãy làm theo hướng dẫn chi tiết trong Trung tâm trợ giúp để chuyển tệp sang máy đọc sách điện tử được hỗ trợ.
