Full-Chip Nanometer Routing Techniques
2007年8月 · Springer Science & Business Media
电子书
102
页
report评分和评价未经验证 了解详情
关于此电子书
At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.
In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.
为此电子书评分
欢迎向我们提供反馈意见。
如何阅读
智能手机和平板电脑
笔记本电脑和台式机
您可以使用计算机的网络浏览器聆听您在 Google Play 购买的有声读物。
电子阅读器和其他设备
如果要在 Kobo 电子阅读器等电子墨水屏设备上阅读，您需要下载一个文件，并将其传输到相应设备上。若要将文件传输到受支持的电子阅读器上，请按帮助中心内的详细说明操作。
