Low Power Interconnect Design
Sandeep Saini
Jun 2015 · Springer
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reportUkadiriaji na maoni hayajahakikishwa Pata Maelezo Zaidi
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This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.
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