Hardware Verification with C++: A Practitioner’s Handbook
Dec 2006 · Springer Science & Business Media
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For Further Reading . . . . . . . . . . . . . . . . . . . . . . . 41 C h a p t e r 4 : A L a y e r e d A p p r o a c h . . . . . . . . . . . 43 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A Whiteboard Drawing . . . . . . . . . . . . . . . . . . . . . . 46 An “ends-in” approach. . . . . . . . . . . . . . . . . . . . . 47 Refining the whiteboard blocks . . . . . . . . . . . . . . . 47 The “Common-Currency” Components . . . . . . . . . . . 48 The Interface Layer in Detail. . . . . . . . . . . . . . . . . . 49 The wire layer . . . . . . . . . . . . . . . . . . . . . . . . . . 50 The agent layer . . . . . . . . . . . . . . . . . . . . . . . . . 52 The transaction layer . . . . . . . . . . . . . . . . . . . . . 53 The Top-Layer Components . . . . . . . . . . . . . . . . . . 54 What is a Test? . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 The Test Component . . . . . . . . . . . . . . . . . . . . . . . 58 The Test Irritator . . . . . . . . . . . . . . . . . . . . . . . . . 60 A Complete Test . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 For Further Reading . . . . . . . . . . . . . . . . . . . . . . . 63 Part II: An Open-Source Environment with C++ . . . . . . 65 C h a p t e r 5 : T e a l B a s i c s . . . . . . . . . . . . . . . . . . . 67 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 What Teal provides . . . . . . . . . . . . . . . . . . . . . . . 68 Teal’s similarity to HDLs . . . . . . . . . . . . . . . . . . . 69 A tiny but complete example . . . . . . . . . . . . . . . . 69 Teal’s Main Components. . . . . . . . . . . . . . . . . . . . . 71 Using Teal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Your C++ test . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 A P r ac titioner ’s Handboo k ix Contents Creating registers . . . . . . . . . . . . . . . . . . . . . . . 74 Working with a reg or vreg . . . . . . . . . . . . . . . . . . 75 Logging Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Using Test Parameters . . . . . . . . . . . . . . . . . . . . . . 79 Accessing Memory . . . . . . . . . . . . . . . . . . . . . . . . . 81 A memory note example . . . . . . . . . . . . . . . . . . . 82 Constrained Random Numbers . . . . . . . . . . . . . . . . . 84 Required initialization . . . . . . . . . . . . . . . . . . . . . 84 Using random numbers. . . . . . . . . . . . . . . . . . . . . 84 Working with Simulation Events and Concurrency . . . . 86 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 For Further Reading . . . . . . . . . . . . . . . . . . . . . . . 88 Chapter 6: Truss: A Standard Verification F r a m e w o r k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 General Considerations . . . . . . . . . . . . . . . . . . . . . 93 Using a language other than C++ . . . . . . . . . . . . . . 93 Keeping it simple . . . . . . . . . . . . . . . . . . . . . . . . 94 Major Classes and Their Roles . . . . . . . . . . . . . . . . .
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About the author
Mike Mintz has more than 20 years of software development experience. Five years ago, he switched back to hardware verification. He has managed groups of software developers and has more than 15 years of C++ programming experience. He implemented C++ verification systems at several companies, using C++, as well languages such as SystemVerilog, Vera and ‘e’.
Robert Ekendahl has a background in ASIC design and more then 12 years experience as a senior verification engineer. Has developed verification system and served as project manager for fortune 100 companies and start-ups with a focus on telecommunication. Has worked in C++ as well as languages such as Verilog, VHDL, C, Vera and ‘e’.
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